1. Field of the Invention
The present invention relates to the interconnecting structure of a semiconductor device and, more specifically, it relates to the cross sectional shape of the interconnection formed on the semiconductor with an insulating film interposed therebetween.
2. Description of the Prior Art
FIG. 1 is a plan view showing the memory portion of a dynamic MOS RAM (random access memory) having a folded bit line structure.
In the figure, the random access memory comprises an active region 4 for storing charges representing information, bit lines 1 formed of a first aluminum interconnecting layers electrically connected with the active region 4 through a contact 5, a cell plate 6 which is to be one electrode of the memory cell capacitor for storing charges representing information and word lines 3 for controlling the reading/writing operation of information represented by charges in the memory cell. A field oxide film is provided between adjacent active regions and the regions are electrically insulated from each other. Namely, the field oxide film is formed around the active region 4. The cell plate 6 is formed outside of the region which is surrounded by the dot-and-dash line, that is, on the field oxide film. In that region where the cell plate 6 is not formed, an MOS transistor having the word line 3 serving as a gate electrode is formed and that region serves as the transfer gate at the time of reading/writing the signal charge. In the folded bit line structure shown in the figure, two bit lines constitute a pair of bit line pair, and one memory cell is connected to every each bit line for one word line.
Description will be given of the information reading operation as an example.
First, one word line is selected and the information stored in the memory cell connected to the said word line 3 is read to the bit line 1. In the folded bit line structure, normally the potential difference between the bit line to which the selected memory cell is connected and the bit line to which the non-selected memory cell is connected (hereinafter referred to as complementary bit line) in one bit line pair is detected to read out the information. Namely, a reference potential appears on the complementary bit line and the potential corresponding to the information stored in the memory cell appears on the selected bit line. The potential difference between bit line and the reference potential on the complementary bit line is enlarged to read out the information.
In the normal reading operation of information, an input signal is applied to one word line 3 to activate the transistor, charges stored in the memory cell is read to the bit line 1 through the contact 5 and this is detected as the amount of potential change, that is, the output signal, in the sense amplifier (not shown) connected to the bit line 1. In this operation, the influences exerted on the output signals by the input signal (from the transistor) due to the length of the interconnection of the bit line 1 from the contact 5 to the sense amplifier cannot be neglected in the device in which the high speed operation is required.
FIG. 2 shows the relation of the operation delay between the input signal and the output signal.
Referring to the figure, the input signal changed from the low level V.sub.L to the high level V.sub.H and the corresponding conversion operation of the output signal from the low level V.sub.L to the high level V.sub.H is shown. As is apparent from the figure, the output signal is not changed immediately from V.sub.L to V.sub.H but is gradually changed to V.sub.H in a certain period time t. Namely, the input signal appears as an output signal after the operation delay by the time t. This time delay is proportional to the time constant (R.times.C=resistance .times.capacitance) of the bit line 1, so that this constant should be made small in order to increase the speed of operation of the device. However, as the device has come to be smaller, the interconnections become thinner and, in addition, the routing of the interconnections are carried out making the interconnections longer. Therefore, the resistance R seems to be increasing.
On the other hand, the presence or absence of the output signal is detected in the sense amplifier as the amount of potential change, as described above. Assuming that the bit line capacitance is C.sub.B and the memory cell capacitance is C.sub.S, the amount of change in the potential appearing at the bit line 9 is a very small value given by C.sub.S /C.sub.B. The bit line capacitance C.sub.B includes the interconnecting capacitance of the bit line itself and the floating capacitance parasitic thereto. The increase in the parasitic capacitance, and therefore the increase in the bit line capacitance C.sub.B extremely reduces the amount of potential change appearing at the bit line 1, making the accurate reading of information difficult.
In view of the foregoing, the decrease of the parasitic capacitance in the interconnecting structure is quite important for the operation characteristics in general and for the accurate reading of the information in the random access memory and the like.
FIG. 3 is a cross sectional view taken along the line III--III of FIG. 1, and FIG. 4 is the cross sectional view taken along the line IV--IV of FIG. 1.
The cross sectional structure will be hereinafter described with reference to FIGS. 3 and 4.
A source region (or a drain region) 9 and a drain region (or a source region) 10 are formed in the field region of a semiconductor substrate 7 and a cell plate 6 which is to be a capacitor is formed on a portion of the drain region 10 with an insulating film 8 interposed therebetween. A word line 3 which is to be a gate electrode of a switching transistor is formed on that portion between the source region 9 and the drain region 10 which is to be a channel region with an insulating film interposed therebetween and, in addition, a bit line 1 is connected to the source region 9 through a contact 5. The bit line 1 is formed on an interlayer insulating film 11 which is formed to smooth the step on the semiconductor substrate 7 and, an upper insulating film 12 is formed on the entire surface in order to protect the surface of the device. Referring to FIG. 3, parasitic capacitances of the bit line 1 are generated in various portions (reference should be made to the dotted lines). For example, the parasitic capacitances are generated between the bit line 1 and the word line 3, between the bit line 1 and the drain region 10, between the bit line 1 and the cell plate 6, and so on.
Meanwhile, the higher the dynamic RAM becomes integrated, the smaller the device, specifically the memory cell, becomes, and the thinner the interlayer insulating films become between the interconnections, the larger the capacitance of the bit line becomes. If the thickness of the bit line is increased to reduce the area of the lower portion to cope with this situation, the thickness makes the minute processing difficult and, if the width is enlarged to facilitate the minute processing, the capacitances between the cell plate 6 and the bit line 1 or between the bit lines 1 are increased as shown in FIG. 4
As described above, the parasitic capacitance of the bit lines or the like presents an extremely serious problem in increasing the speed of operation and in high integration of the dynamic RAM.
An interconnecting structure of a CMOS DRAM in which the bit line is formed of aluminum and the word line is formed of the two-layer of TaSi.sub.2 /Polysilicon is disclosed in "TECHNOLOGY FOR THE FABRICATION OF A 1 MB CMOS DRAM" by D. S. Yaney et al., 1985 IEDM Technical Paper, pp. 698-701.
However, the disclosure in the above mentioned literature neither decreases the parasitic capacitance of the interconnections nor suggests any method for decreasing the parasitic capacitance. The disclosure does not eliminate the problem which is to be solved by the present invention.